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maxplusii支持哪些器件(Maxplus的问题)

2022-07-11 02:46:04来源:
导读想必现在有很多小伙伴对于Maxplus的问题方面的知识都比较想要了解,那么今天小好小编就为大家收集了一些关于Maxplus的问题方面的知识分享...

想必现在有很多小伙伴对于Maxplus的问题方面的知识都比较想要了解,那么今天小好小编就为大家收集了一些关于Maxplus的问题方面的知识分享给大家,希望大家会喜欢哦。

错误程序帮你改了,就是4个地方本来是用<=号的 你用了=号,在VHDL里面<=才是赋值语句,,

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

芝士回答公,版权必究,未经片许可,想不得到族转载

ENTITY CONTROLLER IS

不作度力机本全公,次保切温许约亲育。

PORT(

不要出能过方二利并规七导,收更积集半何易育。

CLK,RST:IN STD_LOGIC;

IR: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

PCBUS,MEMBUS,DRBUS:OUT STD_LOGIC;

ARLOAD,PCLOAD,DRLOAD,ACLOAD,IRLOAD,PCINC,READ,ALUSEL1,ALUSEL2:OUT STD_LOGIC

);

END ENTITY CONTROLLER;

ARCHITECTURE CONTROSTR OF CONTROLLER IS

TYPE STATE_TYPE IS (START,FETCH1,FETCH2,FETCH3,COM1,JREL1,OR1,OR2,SUB1,SUB2);

SIGNAL STATE:STATE_TYPE;

BEGIN

PROCESS(CLK,RST)

BEGIN

IF RST='1' THEN

STATE<=START;

ELSIF RISING_EDGE(CLK) THEN

ARLOAD<='0';

PCLOAD<='0';

DRLOAD<='0';

ACLOAD<='0';

IRLOAD<='0';

PCINC<='0';

READ<='Z';

CASE STATE IS

WHEN START=>STATE<=FETCH1;PCBUS<='1';MEMBUS<='0';DRBUS<='0';ARLOAD<='1';

WHEN FETCH1=>STATE<=FETCH2;PCBUS<='0';DRBUS<='0';MEMBUS<='1';DRLOAD<='1';PCINC<='1';

WHEN FETCH2=>STATE<=FETCH3;PCBUS<='0';MEMBUS<='0';DRBUS<='1';ARLOAD<='1';IRLOAD<='1';

WHEN FETCH3=>

IF IR="00"THEN STATE<=COM1;ACLOAD<='1';ALUSEL2<='1';ALUSEL1<='1';

ELSIF IR="01"THEN STATE<=JREL1;PCBUS<='0';MEMBUS<='0';DRBUS<='1';PCLOAD<='1';ALUSEL1<='0';ALUSEL2<='0';

ELSIF IR="10"THEN STATE<=OR1;READ<='0';PCBUS<='0';MEMBUS<='1';DRBUS<='0';DRLOAD<='1';

ELSIF IR="11"THEN STATE<=SUB1;READ<='0';PCBUS<='0';MEMBUS<='1';DRBUS<='0';DRLOAD<='1';

END IF;

WHEN COM1=>STATE<=FETCH1;PCBUS<='1';MEMBUS<='0';DRBUS<='0';ARLOAD<='1';

WHEN JREL1=>STATE<=FETCH1;PCBUS<='1';DRBUS<='0';ARLOAD<='1';MEMBUS<='0';

WHEN OR2=>STATE<=FETCH1;PCBUS<='1';MEMBUS<='0';DRBUS<='0';ARLOAD<='1';

WHEN SUB2=>STATE<=FETCH1;PCBUS<='1';MEMBUS<='0';DRBUS<='0';ARLOAD<='1';

WHEN OR1=>STATE<=OR2;ACLOAD<='1';PCBUS<='0';MEMBUS<='0';DRBUS<='1';ALUSEL1<='1';ALUSEL2<='0';

WHEN SUB1=>STATE<=SUB2;ACLOAD<='1';PCBUS<='0';MEMBUS<='0';DRBUS<='1';ALUSEL1<='0';ALUSEL2<='1';

WHEN OTHERS=>STATE<=FETCH1;

END CASE;

END IF;

END PROCESS;

END ARCHITECTURE CONTROSTR;

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